Here, an extraction technique of don't care bits in a test pattern suggested conventionally for detecting a stuck-at fault is described.
FIG. 10 is a schematic diagram of a full-scan sequential circuit in an ordinary logic circuit.
Generally, a semiconductor logic circuit is a sequential circuit in most cases. The sequential circuit is configured to include a combinational circuit portion 1201 constituted by logic elements such as an AND gate, a NAND gate, an OR gate and a NOR gate, and flip-flops 1203 each storing a circuit internal state. In this case, the combinational circuit portion 1201 includes primary input lines (PIs), pseudo primary input lines (PPIs) that are flip-flop output lines, primary output lines (POs), and pseudo primary output lines (PPOs) that are flip-flop input lines. Inputs to the combinational circuit portion 1201 include those directly applied from the primary input lines and those applied via the pseudo primary input lines. Further, outputs from the combinational circuit portion 1201 include those directly appearing on the primary output lines and those appearing on the pseudo primary output lines.
However, output lines (pseudo primary input lines) and input lines (pseudo primary output lines) of the flip-flops 1203 of the sequential circuit are usually inaccessible from outside. Due to this, to test the combinational circuit portion 1201 has problems of controllability over the pseudo primary input lines and observability of the pseudo primary output lines.
Full scan design is known as a main method of solving the problems of the controllability and the observability confronted by testing of the combinational circuit portion 1201. The full-scan design means replacing flip-flops by scan flip-flops and generating one or a plurality of scan chains using the scan flip-flops. Operations performed by the scan flip-flops are controlled by a scan enable (SE) signal line. For example, if SE=0, each of the scan flip-flops operates similarly to the conventional flip-flops. If a clock pulse is applied, an output value from each of the scan flip-flops is updated to a value from the combinational circuit portion 1201. Further, if SE=1, one scan flip-flop and another scan flip-flop in the same scan chain form one shift register. If a clock pulse is applied, a new value is loaded to the scan flip-flop through shift-in from the outside and, at the same time, a value currently present in the scan flip-flop is loaded to the outside through shift-out. Normally, the scan flip-flops belonging to the same scan chain share the same scan enable (SE) signal line. The scan flip-flops belonging to different scan chains either share the same scan enable (SE) signal line or use different scan enable (SE) signal lines.
A test is conducted on the combinational circuit portion of a full-scan sequential circuit by repeating scan shift and scan capture. The scan shift is performed in a shift mode in which a scan enable (SE) signal is set to a logic value 1. In the shift mode, one or a plurality of clock pulses is applied and one or a plurality of new values is loaded into the scan flip-flops in each scan chain through shift-in from the outside. At the same time, one or a plurality of values currently present in the scan flip-flops in the scan chain is loaded to the outside through shift-out. The scan capture is performed in a capture mode in which the scan enable (SE) signal is set to a logic value 0. In the capture mode, one clock pulse is applied simultaneously to all the scan flip-flops in one scan chain, and values of the pseudo primary output lines of the combinational circuit portion are loaded into all the scan flip-flops.
The scan shift is used to apply test vectors to the combinational circuit portion 1201 via the pseudo primary input lines and to observe a test response from the combinational circuit portion 1201 via the pseudo primary output lines. The scan capture is used to load the test response from the combinational circuit portion 1201 into the scan flip-flops. By repeating the scan shift and the scan capture for all the test vectors, the combinational circuit portion can be tested. A test method of this type is called “scan testing”.
In the scan testing, application of test vectors to the combinational circuit portion 1201 includes direct application of test vectors from the primary inputs and application thereof by means of the scan shift. Since an arbitrary logic value can be set to an arbitrary scan flip-flop by the scan shift, the problem of the controllability over the pseudo primary input lines is solved. Observation of the test response from the combinational circuit portion 1201 includes observation made directly by the primary outputs and observation made by means of the scan shift. Since an output value from an arbitrary scan flip-flop can be observed by the scan shift, the problem of the observability over the pseudo primary output lines is solved. In this way, according to the scan testing, it suffices to obtain test vectors and an expected test response using an automatic test pattern generation (ATPG) program.
FIG. 11 is a schematic diagram showing a relation between test input and test response.
In FIG. 11, in a case where a don't care bit (X) exists in a test vector, a don't care thereby appears in test response, too. A don't care bit exists because determining only a part of logic values of bits of test input is enough to detect one or a plurality of stuck-at faults. A test vector having a don't care bit is also referred to as a test cube. A test cube can be obtained by ATPG or by don't care bits finding technique. Either logic value 0 or 1 can be freely assigned to a don't care bit.
Several techniques relating to extracting don't care bits are disclosed (Non-Patent Document 1-7). Here, the techniques according to Non-Patent Document 1 and 2 are briefly described.
According to Non-Patent Document 1, a technique based on a method referred to as bit-stripping is described. First, a fault simulation is executed to obtain all the faults F(v) which can be detected by only test vector v Next, the first bit of v is temporarily set as a don't care bit, and examine if F(v) can be actually detected by three value fault simulation. When F(v) can be detected, the bit is kept set as a don't care bit, otherwise the bit is set back to its original value. Don't care bits are extracted by repeating these procedures to all the bits.
According to Non-Patent Document 2, by using a part of procedures of fault simulation and ATPG, as many combinations of don't care bits as possible are obtained, keeping the fault coverage of an initial test pattern. The technique is briefly described below with an example. FIG. 12 is a circuit diagram showing an example of a case of identifying don't care bits in a test pattern.
When an initial test pattern for stuck-at faults is given, some bits in the initial test pattern may be changed to the opposite logic value without losing fault coverage. Such bits can be identified as don't-care bits. The example is shown in FIG. 12. Suppose that a test vector <a, b, c, d>=<1, 0, 0, 1> is given and it detects only the stuck-at 1 fault on signal line e. The test vector <a, b, c, d>=<1, 0, 0, 1> means that signal lines <a, b, c, d> are applied with values <1, 0, 0, 1>, respectively. Since the test vector <a, b, c, d>=<1, 0, 0, 1> has only to detect the stuck-at 1 fault on signal line e, logic value 0 on either signal line b or signal line c is unnecessary and one of the logic values can be changed into a don't-care bit. The necessary condition for detecting a stuck-at fault is to assure fault excitation and fault propagation.
First, considering fault excitation of the circuit in FIG. 12, detecting the stuck-at 1 fault on signal line e requires assigning logic value 0 to signal line e. So either signal line b or signal line c has to be assigned with logic value 0, but the other signal line can be assigned with either logic values 0 or 1 to assure the fault excitation. As a result, the signal line can be turned into a don't-care bit. In this example, signal line c is turned into a don't-care bit.
Next, as for the fault propagation, in FIG. 12, there are two propagation paths (e-f-h and e-g-i) from the fault site e to primary outputs (h and i). When there is a plurality of propagation paths as in this case, a propagation path can be chosen arbitrarily. In this example, the propagation path e-f-h is chosen. To activate this propagation path, the signal line a is needed to be assigned with logic value 1. Thereby, the stuck-at 1 fault on signal line e can be detectable by propagating to the primary output h. Thus, the residual signal line d can be treated as a don't-care bit. The obtained test cube <a, b, c, d>=<1, 0, X, X> is enough to detect the stuck-at 1 fault on line e, just as the test pattern <a, b, c, d>=<1, 0, 0, 1>. As explained, some bits in the test pattern can be changed into don't-care bits without losing fault coverage. With this scheme, a simulation is not carried out on all input bits. Due to this, the scheme of Non-Patent Document 2 is much shorter in test application time than that proposed by Non-Patent Document 1.
Non-Patent Document 1: R. Sankaralingam and N. A. Touba, “Controlling peak power during scan testing,” Proceedings of the IEEE VLSI Test Symposium, pp. 153-159, 2002.
Non-Patent Document 2: S. Kajihara and K. Miyase, “On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits,” ICCAD-2001, pp. 364-369, Nov. 2001.
Non-Patent Document 3: A. El-Maleh and A. Al-Suwaiyan, “An efficient test relaxation technique for combinational & full-scan sequential circuits,” Proceedings of IEEE VLSI Test Symposium, pp. 53-59, April 2002.
Non-Patent Document 4: A. El-Maleh and K. Al-Utaibi, “An efficient test relaxation technique for synchronous sequential circuits,” Proceedings of IEEE VLSI Test Symposium, pp. 179, 185, April 2003.
Non-Patent Document 5: Y. Higami, S. Kajihara, S. Kobayashi, Y. Takamatsu, and, I. Pomeranz, “A method to find don't care values in test sequences for sequential circuits,” Proceedings of IEEE International Conference on Computer Design, pp. 397-399, Oct. 2003.
Non-Patent Document 6: B. Koenemann, et. al., “A smart BIST variant guaranteed encoding,” Proceedings of 10th Asian Test Symposium, pp. 325-330, November 2001.
Non-Patent Document 7: H.-G. Liang, S. Hellebrand, and, H.-J. Wunderlich, “Two-dimensional test data compaction for scan-based deterministic BIST,” Proceedings of IEEE International Test Conference, pp. 894-901, November 2001.